| 摘要 |
A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated 5 circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual 10 voltage node increases,. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup. 20A 20B 20C Power Control 24 Power Gated Block 14 Fig. 4A |
