| 摘要 |
A variable bandwidth filter comprises a first filter branch in parallel with a second filter branch. The first filter branch comprises a first resistance in series with an input and a first output, and N parallel paths across the first output, each path comprising a corresponding capacitor in series with a corresponding switch and a common terminal. The second filter branch comprises a second resistance in series with the input and a second output, and N parallel paths across the second output, each path comprising an RC network in series with a switch and a common terminal. A clock tunes the first and second filter branches to a center frequency by controlling the switches of the first and second filter branches. A combiner produces a difference signal comprising a difference between the output of the first filter branch and the output of the second filter branch to provide a filter output having an adjustable bandwidth with reference to a center frequency. The bandwidth is adjusted by changing a value of at least one resistor or at least one capacitor in one or more of the first filter branch or the second filter branch. |
