| 摘要 |
PROBLEM TO BE SOLVED: To realize effective layout design of signal wiring via a large-capacity macro block within a semiconductor integrated circuit.SOLUTION: A layout design method for a semiconductor integrated circuit including a large-capacity macro block, includes the steps of: performing a hierarchical layout design by composing a macro block designed so as to include correction preparatory cells for implementing a function everywhere in advance, to extract unused preparatory cells and information thereof when the design of the macro block is completed; and using the extracted preparatory cells in an upper layer layout design. The method allows the correction preparatory cells in the macro block to be used in the upper layer layout design, to thereby eliminate the necessity of separately providing the preparatory cells for the upper layer layout design, thereby further reducing an area. |
