发明名称 |
CHANGING A SYSTEM CLOCK RATE SYNCHRONOUSLY |
摘要 |
A system includes a shared memory and a plurality of processor cores communicatively coupled to the shared memory. The system includes a processor core memory and a clock subsystem for providing a clock signal to the shared memory and the plurality of processor cores. Each of the plurality of processor cores executes instructions stored in the processor core memory for synchronously changing the clock rate provided by the clock subsystem to the plurality of processor cores. |
申请公布号 |
US2013339633(A1) |
申请公布日期 |
2013.12.19 |
申请号 |
US201213517618 |
申请日期 |
2012.06.14 |
申请人 |
NAYAK VIJAYKUMAR;POORNA PRAJNA RAGHAVENDRA |
发明人 |
NAYAK VIJAYKUMAR;POORNA PRAJNA RAGHAVENDRA |
分类号 |
G06F1/12;G06F12/00;G06F12/14 |
主分类号 |
G06F1/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|