发明名称 |
CACHE SET SELECTIVE POWER UP |
摘要 |
Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor. |
申请公布号 |
US2013339596(A1) |
申请公布日期 |
2013.12.19 |
申请号 |
US201213524574 |
申请日期 |
2012.06.15 |
申请人 |
PRASKY BRIAN R.;SAPORITO ANTHONY;TSAI AARON;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PRASKY BRIAN R.;SAPORITO ANTHONY;TSAI AARON |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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