发明名称 A FAST MECHANISM FOR ACCESSING 2n±1 INTERLEAVED MEMORY SYSTEM
摘要 <p>A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n + 1) or (2n 1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.</p>
申请公布号 WO2013187862(A1) 申请公布日期 2013.12.19
申请号 WO2012US41855 申请日期 2012.06.11
申请人 INTEL CORPORATION;SHARMA, SAURABH;KOKER, ALTUG;NAVALE, ADITYA 发明人 SHARMA, SAURABH;KOKER, ALTUG;NAVALE, ADITYA
分类号 G06F12/00;G06F12/08 主分类号 G06F12/00
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