DELAY LINE

摘要

The present invention relates to a delay circuit which includes delay cells connected in series. One or more delay cells among the delay cells in the delay circuit includes: a first try state inverter which selectively reverses a forward direction input signal from a first delay cell depending on a control signal and then outputs to the forward direction input terminal of a second delay cell; a second try state inverter which selectively reverses the forward direction input signal depending on the control signal and outputs to the reverse direction input terminal of the first delay cell; a third try state inverter which selectively reverses the reverse direction output signal from the second delay cell depending on the control signal and outputs to the reverse direction input terminal of the first delay cell; and a floating prevention circuit for preventing a floating of the forward direction input terminal of the second delay cell. [Reference numerals] (110) Control signal generating unit