Robust circuit protected against transient perturbations and timing faults

摘要

A circuit comprises a combinatory logic circuit having one input and one output (A). First and second sampling elements (92, 93) are connected to the output (A) and sample this output respectively at the activation of a first and second latching events determined by an event of first and second clock signals (CK). The event of second clock signal (CK) is delayed with respect to the event of a first clock by a delay which is shorter than the clock period. An analysis circuit (95) analyzes the outputs of the first and the second sampling elements and provides an error detection signal. The analysis circuit (95) sets the error detection signal (E) at the pre-determined value if the outputs of the first and second sampling elements (92, 93) are different. The circuit is used in a first operating mode in which the event of a second clock (CK) determining the second latching event is delayed with respect to the event of first clock (CK) determining the first latching event by a delay which is larger than a largest delay of the circuit.