发明名称 |
TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES |
摘要 |
<p>Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.</p> |
申请公布号 |
EP2316040(B1) |
申请公布日期 |
2013.12.18 |
申请号 |
EP20090800722 |
申请日期 |
2009.04.30 |
申请人 |
SYNOPSYS, INC. |
发明人 |
KAPUR, ROHIT;SAIKIA, JYOTIRMOY;UPPULURI, RAJESH;NOTIYATH, PRAMOD;FERNANDES, TAMMY;KULKARNI, SANTOSH;ANBALAN, ASHOK |
分类号 |
G01R31/3185 |
主分类号 |
G01R31/3185 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|