| 摘要 |
An output enable signal generation circuit according to the present invention comprises: an output enable reset signal generator for enabling an output enable reset signal in response to an external clock signal, a DLL locking signal and a reset signal; an output enable reset signal delayer for delaying the output enable reset signal for a set time and outputting the delayed output enable reset signal; a counter for converting the number of toggling operations of the external clock signal into a counted value in response to the output enable reset signal and the delayed output reset signal; a read command delay part for delaying the read command for a set time and outputting the delayed read command; and an output enable signal outputting part for shifting the delayed read command in synchronization with the DLL clock signal under the control of the CAS latency and the counted value and outputting the output enable signal. [Reference numerals] (110) Output enable reset signal generator;(120) Output enable reset signal delayer;(121) Output enable reset signal delay line;(122) Replica model part;(130) Counter;(140) Read command delayer;(150) Output enable signal outputting part |
