发明名称 Systems and methods for reduced latency loop correction
摘要 Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.
申请公布号 US8610608(B2) 申请公布日期 2013.12.17
申请号 US201213415430 申请日期 2012.03.08
申请人 RATNAKAR ARAVIND NAYAK;DZIAK SCOTT M.;XIA HAITAO;LSI CORPORATION 发明人 RATNAKAR ARAVIND NAYAK;DZIAK SCOTT M.;XIA HAITAO
分类号 H03M1/06 主分类号 H03M1/06
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