Virtual extension of buffer to reduce buffer overflow during tracing

摘要

A system is disclosed comprising a processor, a trace module, a second buffer, and a bridge. The trace module has a first buffer configured to receive trace data from the processor at a first clock frequency. The second buffer is configured to receive trace data from the first buffer at a second clock frequency. The bridge is configured to receive trace data from the second buffer and output the trace data received from the second buffer at a third clock frequency. The second clock frequency is greater than the first clock frequency and the third clock frequency.