| 摘要 |
An object of the invention is to reduce the size of a decoder circuit of a display device. A decoder circuit which outputs voltages corresponding to 8-bit digital values includes a predecoder section, which includes an A decoder, B decoder, and C decoder, each of which is configured of a matrix type decoder circuit which carries out a three bits' worth of decoding, and a tournament type decoder circuit which carries out a three bits' worth of decoding, a selection circuit which, having input thereinto three voltages output respectively from the A decoder, B decoder, and C decoder, and applied to three output signal lines, selects two voltages of the three input voltages using a bit with one of the digital values and applies them to two output signal lines, and an intermediate voltage output circuit which, having input thereinto the two voltages selected by the selection circuit, outputs a voltage which is the average of the two voltages. |
