| 摘要 |
The present invention relates to a semiconductor memory device. According to the embodiment of the present invention, the semiconductor memory device includes an I/O circuit for receiving an address and data signals from the outside and a peripheral circuit for activating a chip selection signal according to the address and receiving the address though the I/O circuit. The I/O circuit includes a control pad for blocking and providing a data strobe signal according to the chip selection signal, and an I/O pad for transmitting the data signals to the peripheral circuit responding to the data strobe signal. [Reference numerals] (110) Memory cell array;(121) Address decoder;(122) Reading and writing circuit;(123) Control logic;(124) Global buffer;(130) I/O circuit |
