发明名称 PUCE DE CIRCUITS INTEGRES ET PROCEDE DE FABRICATION.
摘要 <p>An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.</p>
申请公布号 FR2970119(B1) 申请公布日期 2013.12.13
申请号 FR20100061356 申请日期 2010.12.30
申请人 STMICROELECTRONICS (CROLLES 2) SAS 发明人 CHAPELON LAURENT-LUC;CUZZOCREA JULIEN
分类号 H01L21/768 主分类号 H01L21/768
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