发明名称 USE OF CONFORMAL COATING ELASTIC CUSHION TO REDUCE THROUGH SILICON VIAS (TSV) STRESS IN 3-DIMENSIONAL INTEGRATION
摘要 <p>Integrated circuit assemblies, as well as methods for creating the same, are provided. The integrated circuit assembly includes a first chip and a second chip, including respective face surfaces, wherein the first chip and the second chip are bonded in a face-against-face contact configuration. The integrated circuit assembly includes a via disposed to pass through the first chip and the second chip. The via is surrounded by at least one material of the respective first chip and the second chip. A cushion layer encapsulating at least a portion of the via is formed between the via and the at least one material surrounding the via.</p>
申请公布号 WO2013184880(A1) 申请公布日期 2013.12.12
申请号 WO2013US44451 申请日期 2013.06.06
申请人 RENSSELAER POLYTECHNIC INSTITUTE 发明人 MCDONALD, JOHN, F.
分类号 H01L23/48;H01L21/768;H01L25/065;H01L25/16 主分类号 H01L23/48
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