发明名称 MULTIPROCESSOR
摘要 PROBLEM TO BE SOLVED: To allow all processor cores to be collectively subjected to transition to a debug mode without extending a length of wiring even when a number of processor cores is increased.SOLUTION: A multiprocessor 1 comprises: a plurality of debug modules 3; a plurality of processor cores c0 through c3 that is provided corresponding to respective ones of the plurality of debug modules 3 and is debugged by the respective debug modules 3 corresponding thereto; and a plurality of debug ring units 4 that is provided corresponding to the respective ones of the plurality of debug modules 3 and generates debug ring information instructing the plurality of processor cores c0 through c3 corresponding thereto to be subjected to transition to a debug mode. The plurality of debug ring units 4 corresponding to the plurality of debug modules 3 is connected to one another in a ring-shape and transmits debug ring information in turn. The debug ring units 4 receiving the debug ring information output debug transition signals instructing the plurality of processor cores c0 through c3 corresponding thereto to be subjected to the transition to the debug mode to the debug modules 3 corresponding thereto.
申请公布号 JP2013250848(A) 申请公布日期 2013.12.12
申请号 JP20120125899 申请日期 2012.06.01
申请人 TOSHIBA CORP 发明人 USUI HIROYUKI
分类号 G06F11/28 主分类号 G06F11/28
代理机构 代理人
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