| 摘要 |
PROBLEM TO BE SOLVED: To shorten the update time of configuration data.SOLUTION: An FPGA 902 includes: (i) an internal interface section 920 that receives data from an information processing device 1008 via a bus controller 906; (ii) boundary-scan registers R1; and (iii) a register access circuit 924 that controls the values of a register group 912 corresponding to plural I/O pins connected to nonvolatile memory 904, among boundary-scan registers R1, on the basis of a control file F1 having a predetermined format. The control file F1 having the predetermined format is transmitted from the information processing device 1008 to the bus controller 906 by a predetermined data amount including plural words as a unit. A programmable region 930 has there in a storage region larger than the predetermined data amount. The control file F1 is stored in the storage region stores by the unit of the predetermined data amount so that a data buffer section 924 is formed one after another to be transferred to the register access circuit 924. |
