发明名称 |
MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE |
摘要 |
A memory device includes a block of memory cells and a cache. The block of memory cells is not a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided. |
申请公布号 |
WO2013184855(A1) |
申请公布日期 |
2013.12.12 |
申请号 |
WO2013US44390 |
申请日期 |
2013.06.05 |
申请人 |
MOSYS, INC. |
发明人 |
SIKDAR, DIPAK;MILLER, MICHAEL, J.;PATEL, JAY |
分类号 |
G11C7/10;G11C11/41;G11C29/42 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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