发明名称 |
JITTER REDUCTION IN HIGH SPEED LOW CORE VOLTAGE LEVEL SHIFTER |
摘要 |
An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The second supply has a higher voltage than the first supply. |
申请公布号 |
US2013328611(A1) |
申请公布日期 |
2013.12.12 |
申请号 |
US201213494188 |
申请日期 |
2012.06.12 |
申请人 |
KUMAR PANKAJ;PARAMESWARAN PRAMOD;KOTHANDARAMAN MAKESHWAR |
发明人 |
KUMAR PANKAJ;PARAMESWARAN PRAMOD;KOTHANDARAMAN MAKESHWAR |
分类号 |
H03L5/00 |
主分类号 |
H03L5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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