CLOCK GENERATION DEVICE AND METHOD THEREOF

摘要

The present invention discloses a clock generator and a clock generating method. The clock generator according to the present invention includes a reference clock generating part receiving a carrier signal, a multiplexer receiving an output signal of a phase locking loopand an output signal of the reference clock generating part, the phase locking loopreceiving its output signal and an output signal of the multiplexer, and a pause detecting part receiving the carrier signal and outputting a section detection signal to the multiplexer. According to the invention, even in a pause section of the carrier signal, a clock signal without a distortion can be generated by using the phase locking loop (PLL) and the multiplexer (MUX). [Reference numerals] (110) Reference clock generating part;(132) Phase detection part;(134) Charge pump part;(136) Loop filter part;(140) Pause detecting part;(150) Selection signal generating part;(410) Clock selection signal generating part;(AA) Carrier signal