| 摘要 |
A delay fixing loop, generating a DLL clock by controlling a delay of an external clock according to a result of comparing phase differences between the external clock and a feedback clock delaying the DLL clock as much as a model delay value, includes a first delay terminal, a second delay terminal, a phase mixing part, and a slope adjusting part. The first delay terminal generates a first delay clock by extending a delay of the external clock through a plurality of short delayers and a plurality of long delayers connected in series. The second delay terminal generates a second delay clock by extending a delay of the external clock through the short delayers and the long delayers connected in series. The phase mixing part generates the DLL clock by mixing the first and second clocks. The slope adjusting part adds more loading of the first and second delay clocks when the delay of the external clock is controlled through the long delayers included in the first delay terminal. At that time, the first delay clock is more delayed that the second delay clock. [Reference numerals] (300) Phase mixing part;(410) Switching control part;(421) First switch;(422) First capacitor;(431) Second switch;(432) Second capacitor |
