| 摘要 |
In one embodiment, a phase locked loop comprises a phase frequency detector (PFD) configured to detect a phase difference and a frequency difference between inputs of a reference clock signal and a feedback clock signal, and output an up signal and a down signal. A logic gate includes an AND gate wherein one of the up signal or the down signal from the PFD is coupled to an inverted input and the other signal is coupled to a non-inverted input to produce a pulse signal. A time to digital converter (TDC) is coupled to the logic gate wherein the pulse signal output from the AND gate is input to the TDC as an enable signal for the TDC, and wherein the TDC is configured to generate a digital timing signal representing a difference between two edges of the pulse signal. |
