| 摘要 |
A flash memory control circuit including a microprocessor unit, a first interface unit, a second interface unit, a buffer memory, a memory management unit, and a data read/write unit is provided. The memory management unit manages a plurality of flash memory units, wherein each of the flash memory units has a plurality of flash memories, each of the flash memories has a plurality of memory cell arrays, and each of the memory cell arrays at least has an upper page and a lower page. The memory management unit groups the memory cell arrays of the corresponding flash memories into a plurality of data transfer unit sets (DTUSs). The data read/write unit interleavingly transfers data to the flash memory units in units of the DTUSs. Thereby, the flash memory control circuit can transfer the data stably and the usage of the buffer memory can be reduced. |
