发明名称 |
State retention supply voltage distribution using clock network shielding |
摘要 |
An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding. |
申请公布号 |
US8604853(B1) |
申请公布日期 |
2013.12.10 |
申请号 |
US201213480971 |
申请日期 |
2012.05.25 |
申请人 |
JARRAR ANIS M.;SANCHEZ HECTOR;FREESCALE SEMICONDUCTOR, INC. |
发明人 |
JARRAR ANIS M.;SANCHEZ HECTOR |
分类号 |
H03K3/289 |
主分类号 |
H03K3/289 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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