VERTICAL CHANNEL TRANSISTOR WITH SELF ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME

摘要

The present technology relates to a vertical channel transistor suppressing a resistance increase of a vertical gate electrode and a manufacturing method thereof. A semiconductor device manufacturing method of the present technology includes a step of forming a plurality of pillars having a first and second side walls facing each other on a substrate, a step of forming a gate insulating film on the first and second side walls, a step of forming a first gate electrode covering the first side wall and a shield gate electrode covering the second side wall and lower than the first gate electrode on the gate insulating film, and a step of forming a second gate electrode placed between the pillars by being connected to the first gate electrode. The technology can form a self-arranged vertical gate electrode of single gate structure or double gate structure.