| 摘要 |
A flash memory comprising pure logic transistors according to the present invention includes: a memory array having a plurality of WLs and a plurality of BLs such that cells adjacent in a WL direction share the body of a coupling device and the body of an erase device with one another; a high voltage switching part capable of receiving a program or an erase voltage which is three times to four times a voltage in a normal operation range of an individual pure logic transistor and outputting selectively the program or the erase voltage while the individual transistor is operated in the normal operation range; and a buffer and a memory readout circuit necessary for performing a selective refresh operation on a specific WL. The present invention provides an on-chip non-volatile memory structure and a manufacturing method which can be manufactured concurrently on a general logic circuit such as a microprocessor and on a wafer without adding other special manufacturing process. [Reference numerals] (100) Buffer and memory readout circuit;(200) Memory address decoder |
