发明名称 VERTICAL CHANNEL TRANSISTOR WITH SELF-ALIGNED GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME
摘要 A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.
申请公布号 US2013320433(A1) 申请公布日期 2013.12.05
申请号 US201213605550 申请日期 2012.09.06
申请人 CHO HEUNG-JAE;HWANG EUI-SEONG;PARK EUN-SHIL 发明人 CHO HEUNG-JAE;HWANG EUI-SEONG;PARK EUN-SHIL
分类号 H01L21/28;H01L29/78 主分类号 H01L21/28
代理机构 代理人
主权项
地址