发明名称 |
METHOD OF FABRICATING A GATE-ALL-AROUND WORD LINE FOR A VERTICAL CHANNEL DRAM |
摘要 |
<p>A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less.</p> |
申请公布号 |
WO2013180757(A1) |
申请公布日期 |
2013.12.05 |
申请号 |
WO2013US00141 |
申请日期 |
2013.05.24 |
申请人 |
APPLIED MATERIALS, INC. |
发明人 |
CHANG, CHORNG-PING;PING, ER-XUAN;PAN, JUDON, TONY |
分类号 |
H01L21/8242;H01L27/108 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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