发明名称 |
CLOCK TRANSFER CIRCUIT, VIDEO PROCESSING SYSTEM, AND SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
A clock transfer circuit receives input data synchronized with a first clock and outputs the received input data as output data synchronized with a second clock having a different frequency. A write address control unit (23) operates in synchronization with the first clock and supplies a write address to a memory (21). A read address control circuit (24) operates in synchronization with the second clock and supplies a read address to the memory (21). A frequency comparator (30) compares the input data with the output data in the frequency of a predetermined event. Based on this comparison result, clock adjustment units (14, 15) adjust the frequency of the second clock. |
申请公布号 |
WO2013179349(A1) |
申请公布日期 |
2013.12.05 |
申请号 |
WO2012JP03596 |
申请日期 |
2012.05.31 |
申请人 |
PANASONIC CORPORATION;NISHIO, YUUKI |
发明人 |
NISHIO, YUUKI |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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