| 摘要 |
A semiconductor memory apparatus includes a plurality of mats each having a plurality of memory cells coupled to intersections between a plurality of word lines and bit lines which are arranged to cross each other, wherein a word line boosting voltage or negative word line voltage is driven onto a word line, depending on whether the corresponding word line is selected or not, and the negative word line voltage driven to a mat including the selected word line has a lower level than the negative word line voltage driven to a mat which does not include the selected word line. |
