发明名称 |
METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER |
摘要 |
A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process. |
申请公布号 |
US2013323898(A1) |
申请公布日期 |
2013.12.05 |
申请号 |
US201213486050 |
申请日期 |
2012.06.01 |
申请人 |
WANG CHUNG-MING;LIU YU LUN;LIU CHIA-CHU;CHANG YA HUI;CHEN KUEI-SHUN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
WANG CHUNG-MING;LIU YU LUN;LIU CHIA-CHU;CHANG YA HUI;CHEN KUEI-SHUN |
分类号 |
H01L21/28;H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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