RF BUFFER CIRCUIT WITH DYNAMIC BIASING

摘要

PROBLEM TO BE SOLVED: To provide an RF buffer circuit which reduces peak gate-to-drain voltages and allows improved reliability of MOS devices in a configuration amenable to low phase noise and low power consumption.SOLUTION: An RF buffer circuit for a voltage controlled oscillator (VCO) includes dynamic biasing circuitry to selectively flip the phase of the output voltage waveform. In a CMOS implementation, a PMOS/NMOS pair is employed in an output path. During a high (voltage) swing mode condition, the phase of the output is flipped such that the output waveform is in phase with the voltages appearing at the gates of the PMOS/NMOS pair.