| 摘要 |
A DLL clock generation part comprises a delay line generating a DLL clock by retarding the clock with a delay time after the phases of the clock and a feedback clock are compared to determine the delay time of the delay line. A delay detection part enables a delay detection signal when the delay time is a set time by detecting the delay time of the delay line. A power down control part resets the DLL clock generation part when the delay detection signal is disenabled and prevents the DLL clock generation part from being reset in a self refresh operation in the power down mode. [Reference numerals] (110) Buffer;(120) Delay line;(130) Replica;(140) Phase comparison part;(150) Delay control part;(200) Output enable signal generation part;(300) Delay detection part;(400) Power down control part |
