发明名称 GENERATION OF ANALOG VOLTAGE USING SELF-BIASED CAPACITIVE FEEDBACK STAGE
摘要 Analog voltage drain with reduced current drain is achieved by a new capacitive-divided feedback architecture. During the operational phase an op amp monitors a capacitively-divided fraction of the output voltage, and drives a current sink or source accordingly; during an initial phase the output is forced to the correct value by a different circuit, while the opamp is connected to self-tune itself in a way which removes DC offset effects.
申请公布号 KR101336849(B1) 申请公布日期 2013.12.04
申请号 KR20097016092 申请日期 2007.12.28
申请人 发明人
分类号 G11C5/14;G11C16/26;G11C16/30 主分类号 G11C5/14
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