| 摘要 |
<p>The present technology relates to a buffer control circuit of a semiconductor memory device. The buffer control circuit includes: a delay unit which determines a delay quantity in response to a plurality of command latencies and generates a plurality of delay signals by delaying a command according to a clock; and a buffer control signal generating unit which generates a buffer control signal by receiving the command latencies and the delay signals. [Reference numerals] (100) Command decoder;(200) Buffer control unit</p> |
