发明名称 |
Reducing store-hit-loads in an out-of-order processor |
摘要 |
<p>A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.</p> |
申请公布号 |
GB2494542(B) |
申请公布日期 |
2013.12.04 |
申请号 |
GB20120016172 |
申请日期 |
2012.09.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BRIAN KONIGSBURG;DAVID MUI;DAVID STEPHEN LEVITAN;BRIAN ROBERT MESTAN |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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