| 摘要 |
<p>Memory apparatus 12 includes a plurality of gated phase-change memory cells 15 having two or more programmable cell-states, the cells 15 each having a gate Gn and being arranged in series between a source and drain. The apparatus further includes a bias voltage generator 21, for applying a bias voltage to the gate of each cell 15, and a controller 22. The controller 22 is adapted to control the bias voltage generator 21, in a write operation for programming the state of a cell 15, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation. Application of the first bias voltage to a cell 15 reduces the cell resistance such that application of a programming signal (via R/W signal generator 20) between said source and drain affects programming of the addressed cell only. The same bias voltage control mechanism can be used to address cells for read operations.</p> |
