发明名称 |
Method of circuit design yield analysis |
摘要 |
A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value. |
申请公布号 |
US8601416(B2) |
申请公布日期 |
2013.12.03 |
申请号 |
US201213535709 |
申请日期 |
2012.06.28 |
申请人 |
KUO CHIN-CHENG;HU WEI-YI;KUAN JUI-FENG;CHENG YI-KAN;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
KUO CHIN-CHENG;HU WEI-YI;KUAN JUI-FENG;CHENG YI-KAN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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