发明名称 |
Equivalent waveform model for static timing analysis of integrated circuit designs |
摘要 |
In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation. |
申请公布号 |
US8601420(B1) |
申请公布日期 |
2013.12.03 |
申请号 |
US20100960387 |
申请日期 |
2010.12.03 |
申请人 |
KELLER IGOR;PHILLIPS JOEL R.;CHEN JIJUN;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
KELLER IGOR;PHILLIPS JOEL R.;CHEN JIJUN |
分类号 |
G06F17/50;G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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