发明名称 |
Arithmetic processing apparatus, arithmetic processing system, and arithmetic processing method which utilize limitation information to perform enhanced arithmetic processing |
摘要 |
An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored. |
申请公布号 |
US8601238(B2) |
申请公布日期 |
2013.12.03 |
申请号 |
US20100787013 |
申请日期 |
2010.05.25 |
申请人 |
YAMANE KENJI;KANO TSUYOSHI;TAKAHASHI MASAHIRO;SONY CORPORATION |
发明人 |
YAMANE KENJI;KANO TSUYOSHI;TAKAHASHI MASAHIRO |
分类号 |
G06F9/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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