发明名称 SECOND LEVEL INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME
摘要 Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.
申请公布号 KR20130130708(A) 申请公布日期 2013.12.02
申请号 KR20137010817 申请日期 2011.09.20
申请人 GEORGIA TECH RESEARCH CORPORATION 发明人 RAJ PULUGURTHA MARKONDEYA;KUMBHAT NITESH;SUNDARAMAN VENKY;TUMMALA RAO R.;QIN XIAN
分类号 H01L23/48 主分类号 H01L23/48
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