| 摘要 |
The present invention relates to a gate driving circuit capable of preventing multi-outputs by a coupling phenomenon and comprises; an output clock generator which sequentially outputs output clock pulses of i (i is natural number over 2); a control clock generator which sequentially outputs control clock pulses of j (j is natural number over 2); and a shift resister which sequentially outputs multiple scan pulses by receiving the output clock pulses of i from the output clock generator and the control clock pulses of j of the control clock generator. The output clock pulses of i is formed of multiple output pulses which are periodically outputted and the control clock pulses of j is formed of multiple control pulses which are periodically outputted. The control pulses included in each control clock pulses of j is synchronized with the output pulses included in at least one output clock pulse. [Reference numerals] (CCG) Control clock generator;(OCG) Output clock generator;(SR) Shift register |
