| 摘要 |
The technology is for reducing test time of a memory. The memory includes one or more data pads, a cell array including a plurality of memory cells, one or more global lines delivering data accessed in the cell array, and a data delivery part operated in one of first and second modes set in response to an inputted address, delivering data inputted to the data pads to the global lines when operated in the first mode, and delivering generated data to the global lines when operated in the second mode. [Reference numerals] (210) Cell array;(230) Address decoder;(240) Data input unit |
