发明名称 WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a wafer level package capable of reducing a process cost without the need for increasing the height of a metal post and allowing the metal post to play a role of a buffer to deformation of the package due to a CTE mismatch between the wafer level package and a wiring substrate by forming the metal post with a concave side surface.SOLUTION: There is provided a wafer level package including: a wafer 10 having a die pad 11; a redistribution line 13 formed to be connected on a top surface of the die pad 11; metal posts 15 each connected to a top surface of the redistribution line 13 and having a concave side surface; and a molding resin 14 formed between the metal posts 15.
申请公布号 JP2013239758(A) 申请公布日期 2013.11.28
申请号 JP20130184840 申请日期 2013.09.06
申请人 SAMSUNG ELECTRO-MECHANICS CO LTD 发明人 LEE SEUNG SEOUP;SUN YI
分类号 H01L23/12 主分类号 H01L23/12
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