| 摘要 |
The invention relates to a device for testing and monitoring digital circuits in order to detect delay errors affecting a signal D received directly at the input of a toggle called primary sampling member (100, 200), providing a first value D1 of the signal D and receiving a first clock signal (105a), said device comprising at least: a scan logic module (120) having a first input for receiving the signal "D", a second input for receiving a signal "scan in", and a third input for receiving a signal "scan enable" (103) suitable for selecting the operation mode of the test device in a scan or functional mode, an output (120s) connected to a secondary sampling member (110) providing a second sampled signal D2 of the signal D after passing through the scan logic module and receiving a second clock signal (105b), and a comparison module (150) for comparing the signal D1 and the signal D2 and generating an alert or error signal. |
