| 摘要 |
<p>A glitch circuit includes an SR flip-flop where a received input clock is operatively coupled to set and reset inputs of the flip-flop, respectively. A configurable delay circuit receives an input signal, and an output of the delay circuit provides a delayed signal. The configurable delay circuit includes a plurality of switchable taps, each providing an increment of delay to the input signal. The delay circuit input is operatively coupled to an output of the flip flop, and an output of the delay circuit is operatively coupled to the inputs of the flip- flop. The glitch circuit captures a first signal transition of the input clock and blocks all other transitions from propagating through the flip-flop during a selected delay period so as to provide on an output of the flip-flop, the glitch-free output clock.</p> |
