| 摘要 |
PROBLEM TO BE SOLVED: To suppress a malfunction due to parasitic resistance of metal wiring patterns on a semiconductor integrated circuit device while suppressing increase in a chip area.SOLUTION: A dummy PT7 having a recess or projection in an area corresponding to wiring PT1 is generated; the dummy PT7 is reduced in size by a predetermined value to generate a reduced figure 8; the reduced figure 8 is enlarged by a predetermined value to generate dummy wiring PT9; a rectangular figure 10 with an outer periphery used as one side is generated; the rectangular figure 10 is reduced in size by a predetermined value to generate a reduced figure 11; the reduced figure 11 is logically subtracted from the dummy wiring PT9 to generate via formation candidates PT12 and 13; a rectangular figure 13 and polygonal figure 12 are extracted out of them; sides 16a, 16b, and 17 extending in a direction orthogonal to one direction in the polygonal figure 12 are extracted; rectangular figures 18a, 18b, and 19 extending in one direction with the sides 16a, 16b, and 17 used as one sides are generated; and vias 20 are arranged within the rectangular figures 13, 18a, 18b, and 19. |
