发明名称 Memory Management Scheme and Apparatus
摘要 A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.
申请公布号 US2013318322(A1) 申请公布日期 2013.11.28
申请号 US201213481903 申请日期 2012.05.28
申请人 SHETTY VARUN;DAS DIPANKAR;CHOUDHURY DEBJIT ROY;REDDY ASHANK;LSI CORPORATION 发明人 SHETTY VARUN;DAS DIPANKAR;CHOUDHURY DEBJIT ROY;REDDY ASHANK
分类号 G06F12/06 主分类号 G06F12/06
代理机构 代理人
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