发明名称 Reception circuit, information processing apparatus, and control method
摘要 A reception circuit (301) that receives data by serial communication in a plurality of lanes and includes a plurality of error checking units (323) each of which checks presence of an error in the received data, a plurality of memories (327) each of which stores the received data, and a processing unit (341) that reads the received data from the plurality of memories, and outputs a read data. The lanes include a redundant lane that transmits redundant data, the received data is stored in a first area of a plurality of areas included in each of the memories, and other received data received next to the received data is stored in a second area. When there is an error in any one of the pieces of received data stored in the respective first areas, the processing unit generates correct data using the redundant data stored in the first area, and outputs it.
申请公布号 EP2645613(A3) 申请公布日期 2013.11.27
申请号 EP20130159152 申请日期 2013.03.14
申请人 FUJITSU LIMITED 发明人 TAKEHARA, MASARU
分类号 H04L1/00 主分类号 H04L1/00
代理机构 代理人
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